1. Field
This application relates to a fractional frequency divider PLL device employing ΣΔ modulation, more particularly, it relates to setting a frequency division value in response to an output signal outputted from a ΣΔ modulator.
2. Description of Related Art
A PLL circuit disclosed in Japanese Patent Publication No. 2004-80404 is shown in FIG. 8. The PLL circuit serves as a fractional NPLL frequency synthesizer (fractional frequency divider PLL device) in which a frequency division value of a comparison frequency divider that constitutes a PLL group is a fractional number.
A ΣΔ modulator 80 is fed a comparison signal fp. Then, the ΣΔ modulator 80 operates by employing the comparison signal fp as a clock signal, to output a Bit Stream of pseudo random numbers to an adder 90, as an output signal prs. For instance, if the ΣΔ modulator 80 has a three-order circuit configuration, the output signal prs becomes random numbers that vary between −3 through +4.
The adder 90 is fed a fixed frequency division value N. Then, the adder 90 adds the output signal prs to the fixed frequency division value N, and outputs the result to the comparison frequency divider 40. The comparison frequency divider 40 performs a frequency division operation using a frequency division value that varies between N−3 through N+4.
Here, the output signal prs outputted from the ΣΔ modulator 80 is random numbers including positive and negative values including value 0 thereinbetween. The frequency division value of the comparison frequency divider 40 is subjected to an arithmetic operation in accordance with this random number. In this case, if the output signal prs is random numbers of both positive and negative polarities, the arithmetic operations inevitably become complicated. This is due to the fact that both an addition operation and a subtraction operation are required depending on the random numbers. Here, adder 90 is provided and is adapted to add a fixed frequency division value N to the output signal prs. As a result, it becomes possible to input only positive values to the comparison frequency divider 40, which thus helps simplify arithmetic operations. The adder 90 has the role of shifting the random values of the output signal prs stretching over positive and negative values to non-negative random values, with the fixed frequency division value N used as an offset value.